A standard ECL output gate with an ECL cutoff driver circuit is illustrated in FIG. 1. The basic ECL gate is a differential gate provided by the gate transistors Q1 and Q3. In this example gate transistor Q1 provides an input transistor element for receiving input signals of high and low potential. Gate transistor Q3 provides a reference transistor element to which a reference voltage signal is applied at an intermediate reference voltage level between the high and low potential input signal levels. The emitter terminals of differential gate transistors Q1 and Q3 are coupled together at a common emitter node coupling. Current sink I1 is coupled between the common emitter node coupling and the low potential level power rail designated V.sub.EE.
The current sink I1 is typically a current source transistor element with a tail resistor in its emitter current path for generating the sink current or tail current. A bias voltage generator, not shown, provides the current source voltage applied to the base of the current source transistor element of the current sink I1.
The ECL differential gate transistor elements Q1 and Q3 provide alternative current paths through respective collector path swing voltage resistors R1 and R2 which are in turn coupled to the high potential level power rail. In this example the high potential level power rail V.sub.CC is at ground potential, and is also designated GND. Typically the swing voltage resistor elements R1 and R2 have substantially equal resistance. Current sink I1 generates the ECL differential gate current in one of the alternative current paths through either of the swing resistors R1 or R2 according to the input signal IN at the base of input transistor element Q1. Because the inverting output is selected for use in this prior art example of FIG. 1, the input signal may be previously inverted to provide an inverted input signal DN for a true output signal at output OUT.
Typical ECL gates may also be constructed according to the differential signal input configuration with differential base input circuits. In the differential signal input ECL gate circuit configuration, the differential gate transistors Q1 and Q3 constitute differential input transistors for complementary inputs IN and DN rather than functioning as an input transistor element and reference transistor element as illustrated. Either type of gate is referred to herein as an ECL differential gate or simply a differential gate or ECL gate.
As further shown in FIG. 1 the ECL gate output signals are taken from the collector node of gate transistor Q1. The collector node is an output switching node which provides output signals of high and low potential through output buffer emitter follower transistor element Q5 to the output OUT. While the collector node of gate transistor Q1 provides the true output signal for an inverted input signal DN, a complemented output signal, not shown, may also be taken from the collector node of gate transistor Q3.
The conventional output cutoff driver circuit for the ECL output differential gate is provided by an output enable (OE) differential gate. The OE differential gate includes OE gate transistor elements Q2 and Q4 in which transistor element Q2 provides the OE input transistor element or cutoff driver transistor element, and transistor element Q4 provides the OE reference transistor element. The OE gate transistor elements Q2 and Q4 are coupled together at a common emitter node coupling, and current sink I2 is coupled between the common emitter node coupling of OE gate transistors Q2 and Q4 and the low potential power rail V.sub.EE. OE input signal transistor element Q2 is a multiemitter transistor element with emitter nodes coupled respectively to current sinks I1 and I2 for supplying both current sinks during the cutoff state as hereafter described.
During normal switching operation of the ECL output gate and the output switching node of gate transistor element Q1, the OE signal is low and OE gate transistor element Q2 is off. The OE gate transistor element Q4 therefore carries the tail current for current sink I2. For the cutoff state, the OE signal is high and OE gate transistor Q2 turns on. With transistor element Q2 conducting, the multiemitter currents satisfy both the current sinks I1 and I2, turning off transistor elements Q3 and Q4. The total sinking current through both current sinks I1 and I2 is forced through load resistor element R1. The abnormally large current causes a large voltage drop across resistor element R1. As a result the voltage level at the collector node of input transistor Q1, and the output OUT, drops below the cutoff potential level approaching a load termination voltage V.sub.TT of, e.g. -2 v. The ECL output OUT is therefore held in the cutoff or high impedance state for applications with multiple ECL output gates on a common bus. In common bus applications, one ECL output gate may be in the active switching mode while the others are held in the cutoff or high impedance state.
One disadvantage of the conventional ECL output gate cutoff driver circuit is the large power dissipation required in the cutoff state. Power dissipation increases as the number of output gates increases, forcing an increasing number of large currents through load resistors. A high power OE driver is also required to drive multiple bit circuits for multi-bit output gates such as hex-buffers or octal buffers.
Another disadvantage of the conventional ECL output gate cutoff driver circuit is that an extra output buffer stage is required if the differential output gate is incorporated in a latch circuit. This is because the feedback signal which holds the latched data signal is also taken from the collector node or output switching node for example of transistor Q1. The feedback signal and latched data bit may be lost in the cutoff state if the cutoff driver circuit is applied directly to a differential gate in the latch circuit. In the cutoff state the output switching node and output are forced to a cutoff low potential level. If the starting output logic signal level were at high potential followed by transition to the cutoff state, the latched date signal would be lost upon transition to the cutoff state. As a result an additional ECL differential gate output buffer stage is required to accommodate the ECL cutoff driver circuit separate from the latch circuit with an additional stage delay.
By way of example a prior art TTL to ECL latch circuit is illustrated in FIG. 2. The TTL input data signals are received at the input buffer stage for sequential input to the flip-flop master latch and slave latch sequential stages. With the clock input signal CLK low the date progresses with delay through the master latch and slave latch stages to the output buffer stage. With the OE signal input low an ECL compatible data output signal is provided. With a clock high signal at the CLK input to the latch stages, the propagating data signals are latched for temporary storage. With an OE signal high at the OE input to the output buffer, the ECL output and output buffer differential gate are held in the cutoff state.
The logical contents of the slave latch are shown in simplified form in FIG. 2A. The slave latch circuit incorporates feedback circuits between the logic gates for holding latched data. The data output node also forms a feedback node for one of the feedback circuits. A cutoff driver applied directly at this output and feedback node would interfere in the feedback circuit. For example with a high level signal at the data output node and feedback node of the slave latch followed by an OE high signal to a cutoff driver incorporated directly into the slave latch circuit, the output node and feedback node are both pulled down to the cutoff condition with loss of the previous state and stored data signal of the latch. For this reason the separate output buffer stage for the OE cutoff driver circuit is required with additional stage delay as illustrated in FIG. 2.